Analog circuits • Digital logic • ADC and DAC • Power supplies • PCB and debugging • 2026

Electronics Engineer Interview Questions

32 questions What each one tests, an answer frame, a spoken answer 34 min read

This page is for electronics engineers, from freshers to people who have shipped several boards. Hardware interviews usually mix circuit theory you can work on a whiteboard, practical questions about power supplies, layout and test equipment, and stories about boards that did not work the first time. Expect to be asked to calculate something small, like a gain or a cutoff frequency, and to explain your thinking out loud. Each question shows what the interviewer is really checking, a shape for your answer and a sample you could say. Replace the stories with your own boards before the day.

Search all questions by round, difficulty and level, or save the ones you want to practise.

Motivation 3 questions

Easy Screening round Fresher, Mid-level Practice question

1. Walk me through how you got into electronics and what kind of hardware work you want to be doing next.

What the interviewer is really testing:
Whether your interest is real and hands-on, and whether the work you want matches what this team actually does.
Answer frame:

Spark: the first thing you built or fixed that pulled you in.

Growth: the course, project or job where you got serious.

Next: the kind of circuits or products you want to work on, and why here fits.

Sample spoken answer:

"I started by repairing things at home, mostly chargers and speakers, and I was hooked the first time I found a dead capacitor and the thing worked again. In college I leaned toward analog and power, and my final-year project was a small battery charger with its own PCB, which taught me more than any exam did. In my last role I worked on sensor boards, doing schematics, bring-up and a lot of debugging on the bench. What I want next is more ownership of a board from requirement to production, especially the power and analog front end. That's why this role interested me, since your products seem to need both."

Red flag to avoid:

A vague love of 'technology' with nothing you have actually built, measured or fixed.

They may ask next:
  • Which part of hardware work do you enjoy least?
  • What's a circuit you built outside of work or study?
Say it in 60 seconds
Easy Screening round Fresher, Mid-level, Senior Practice question

2. What do you know about the products we build, and which part of their electronics would you most like to work on?

What the interviewer is really testing:
Whether you looked at the company's actual hardware and can connect your skills to a specific part of it.
Answer frame:

What they make: the products and the environment they run in.

What that means electrically: power source, noise, safety or size limits you'd expect.

Where you fit: the block you'd most like to own and the experience behind it.

Sample spoken answer:

"From your product pages, you make monitoring units that run in factories, powered from a 24 volt industrial supply and talking back over a wired bus. That tells me the electronics have to cope with noisy power, long cables and a lot of electrical interference, and they need to run for years without anyone touching them. The part I'd most like to work on is the power input and the interface circuits, the protection, filtering and the transceivers, because that's where industrial boards tend to fail. I've done input protection and a buck supply on my last board, so I'd be building on something I already know rather than starting cold."

Red flag to avoid:

Repeating the company slogan without any thought about what the circuits inside must handle.

They may ask next:
  • What failure would you expect to see most often in the field for a product like ours?
  • What would you want to learn in your first month here?
Say it in 60 seconds
Medium Screening round Fresher, Mid-level, Senior Practice question

3. Tell me about the board on your resume you're proudest of: what it does, which blocks you designed yourself, and what you'd change next time.

What the interviewer is really testing:
Whether you can explain your own design clearly, separate your work from the team's, and look back on it critically.
Answer frame:

Purpose: what the board does and its main constraints.

Your part: the specific blocks you designed and the key choices.

Hindsight: one or two things you would do differently on the next revision.

Sample spoken answer:

"The one I'm proudest of is a data logger board with four analog inputs, a microcontroller and a buck converter running from a 12 volt input. I did the full analog front end, which was op-amp buffers, anti-aliasing filters and input protection, plus the power supply. I also did the first layout pass, and a senior engineer reviewed it. It worked on the first spin apart from one footprint error on a connector. If I did it again, I'd put the ADC reference on its own filtered supply, because we saw a little noise from the digital side, and I'd add more test points. We ended up soldering wires on to probe signals during bring-up."

Red flag to avoid:

Describing the whole team's board as if you did everything, or saying you would change nothing.

They may ask next:
  • How did you choose the op-amp for that front end?
  • What did the footprint error teach you about your review process?
Say it in 60 seconds

Analog Circuits 4 questions

Easy Technical round Fresher Practice question

4. What happens in a PN junction diode when you forward and reverse bias it, and when would you use a Zener instead of an ordinary diode?

What the interviewer is really testing:
Whether you understand the basic device, not just the symbol, and know what a Zener is actually for.
Answer frame:

Forward bias: the barrier shrinks and current flows once you pass roughly 0.6 to 0.7 volts for silicon.

Reverse bias: the depletion region widens and only a tiny leakage current flows until breakdown.

Zener use: built to break down at a set reverse voltage, so it's used for clamping and simple references.

Sample spoken answer:

"In a PN junction there's a depletion region at the boundary that acts like a barrier. When I forward bias it, positive on the P side, that barrier shrinks, and once I'm past about 0.6 to 0.7 volts for a silicon diode, current rises steeply. Reverse bias widens the depletion region, so only a tiny leakage current flows. If the reverse voltage gets high enough, the diode breaks down. An ordinary rectifier isn't meant to live there, but a Zener is designed to break down at a specific voltage and hold it fairly steady. So I'd use a Zener to clamp a signal, protect an input, or make a rough reference with a series resistor. For precise references, I'd use a proper reference IC."

Red flag to avoid:

Saying a reverse-biased diode conducts nothing at all and has no breakdown, or treating a Zener as a precision reference.

They may ask next:
  • Why would you pick a Schottky diode over a normal silicon diode?
  • How do you size the series resistor for a Zener clamp?
Say it in 60 seconds
Medium Technical round Fresher, Mid-level Practice question

5. You need to switch a 12 volt relay coil from a 3.3 volt microcontroller pin. Would you use a BJT or a MOSFET, and what else goes in the circuit?

What the interviewer is really testing:
Whether you know how each transistor is driven, can size the drive, and remember the flyback diode.
Answer frame:

BJT: current-driven; size the base resistor so it saturates hard.

MOSFET: voltage-driven; pick one fully on at 3.3 volts of gate drive, add a gate pull-down.

Flyback diode: across the coil to catch the voltage spike at turn-off.

Sample spoken answer:

"Either can work, so I'd start from the coil current. A BJT is current-controlled, so for an NPN low-side switch I'd pick a base resistor that pushes enough current to saturate it well, not just the collector current divided by the typical gain. A MOSFET is voltage-controlled and draws current only while the gate charges, which is nice from a microcontroller pin, but I must pick a logic-level part whose on-resistance is specified at 2.5 or 3.3 volts on the gate, not just look at the threshold voltage. I'd add a pull-down on the gate so the relay stays off while the pin floats during reset. In both cases I put a diode across the coil, cathode to the 12 volt side, because the coil's current can't stop instantly and would otherwise spike the transistor."

Red flag to avoid:

Forgetting the flyback diode, or choosing a MOSFET by its threshold voltage alone.

They may ask next:
  • The flyback diode makes the relay release slowly. How would you speed that up?
  • Why isn't the gate threshold voltage enough to tell you the MOSFET will switch fully?
Say it in 60 seconds
Easy Technical round Fresher, Mid-level Practice question

6. An op-amp is wired as a non-inverting amplifier with a 90k feedback resistor and 10k to ground. What's the gain, and what limits it in a real circuit?

What the interviewer is really testing:
Whether you can do the basic calculation from the ideal rules and also know where a real op-amp stops behaving ideally.
Answer frame:

Ideal rules: no input current, and with negative feedback the inputs sit at the same voltage.

Gain: one plus Rf over Rg, so 10.

Real limits: gain-bandwidth product, slew rate, output swing and input offset.

Sample spoken answer:

"Using the ideal rules, no current flows into the inputs, and with negative feedback the output drives the inverting input to match the non-inverting one. The divider sets the inverting input at the output times 10k over 100k, so the output must be ten times the input. The gain is one plus 90k over 10k, which is 10. In a real part, a few things limit that. The gain-bandwidth product means a 1 megahertz op-amp at a gain of 10 only gives about 100 kilohertz of bandwidth. Slew rate limits how fast large signals can change. The output can't swing all the way to the rails unless it's a rail-to-rail part, and input offset voltage gets multiplied by the gain too."

Red flag to avoid:

Getting the gain as 9 by using the inverting formula, or assuming the op-amp gives that gain at any frequency.

They may ask next:
  • What's the gain if you move the input to the other side and make it inverting?
  • Why might this amplifier oscillate when it drives a long cable?
Say it in 60 seconds
Medium Technical round Fresher, Mid-level Practice question

7. Design a simple RC low-pass filter with a cutoff near 1 kHz. What values would you pick, and what happens to signals above the cutoff?

What the interviewer is really testing:
Whether you know the cutoff formula, can choose sensible real values, and understand roll-off and loading.
Answer frame:

Formula: cutoff is 1 over 2 pi R C.

Values: pick a standard capacitor, then solve for R, keeping R sensible for the source and load.

Response: minus 3 dB at cutoff, then falling 20 dB per decade, with loading as the practical catch.

Sample spoken answer:

"The cutoff of a first-order RC filter is 1 over 2 pi R C. I'd start with a standard capacitor, say 100 nanofarads, and solve for R, which comes to about 1.6 kilohms. That gives a cutoff just under 1 kilohertz. At the cutoff the output is 3 dB down and the phase has shifted by 45 degrees. Above it, the output falls by 20 dB per decade, so a signal at 10 kilohertz comes out at roughly a tenth of its amplitude. The practical catch is loading. The source impedance adds to R, and whatever the filter drives sits in parallel with C, so if the load is heavy I'd buffer it with an op-amp. If I need a steeper roll-off, I'd use an active second-order filter rather than stacking plain RC stages."

Red flag to avoid:

Getting the formula without the 2 pi, or ignoring what the filter is driving.

They may ask next:
  • Why does cascading two identical RC stages not give you a clean second-order response?
  • How would you make a high-pass filter from the same parts?
Say it in 60 seconds

Digital Logic 4 questions

Medium Technical round Fresher, Mid-level Practice question

8. What's the difference between a latch and a flip-flop, and how would you divide a clock by four using D flip-flops?

What the interviewer is really testing:
Whether you understand level versus edge triggering and can build a simple counter, including its weakness.
Answer frame:

Latch: level-sensitive, transparent while enable is active.

Flip-flop: edge-triggered, samples input only on the clock edge.

Divider: feed Q-bar back to D to divide by two, chain two stages to divide by four.

Sample spoken answer:

"A latch is level-sensitive. While its enable is active, the output follows the input, and it holds when enable goes inactive. A flip-flop is edge-triggered, so it only samples its input on the clock edge, which is why synchronous designs use flip-flops. To divide by two, I take a D flip-flop and feed its inverted output back to D. Every rising edge it toggles, so the output runs at half the clock. If I clock a second one from the first stage's output, I get divide by four. That's a ripple counter, and its weakness is that each stage adds delay, so the outputs don't change at exactly the same moment. If I decode those outputs, I can get glitches, so for anything wider I'd use a synchronous counter where every flip-flop shares one clock."

Code:
CLK --> [D FF 1] Q1 --> clock of [D FF 2] Q2
          D1 = not Q1          D2 = not Q2
Q1 = CLK / 2,  Q2 = CLK / 4
Red flag to avoid:

Saying a latch and a flip-flop are the same thing, or not knowing why ripple counters glitch.

They may ask next:
  • How would you make a divide-by-three with a roughly even duty cycle?
  • Why do designers avoid latches in most synchronous logic?
Say it in 60 seconds
Easy Technical round Fresher Practice question

9. Why are NAND and NOR called universal gates? Show me how you'd build a NOT, an AND and an OR using only NAND gates.

What the interviewer is really testing:
Whether you can work with Boolean logic on the spot, including De Morgan's law, rather than just reciting truth tables.
Answer frame:

Universal: any logic function can be built from NAND alone, or from NOR alone.

NOT and AND: tie a NAND's inputs together to invert; a NAND followed by that inverter is an AND.

OR: invert each input first, then NAND them, which is De Morgan's law.

Sample spoken answer:

"They're called universal because you can build any logic function from just one of them, so in principle a whole design could use a single gate type. With NAND, a NOT is easy. I tie both inputs together, so NAND of A with A is just not A. An AND is a NAND followed by that inverter, so two gates. For OR, I use De Morgan's law. A or B is the same as not the result of not A and not B, so I invert each input with a NAND and feed both into a third NAND. That's three gates. An XOR takes four. In CMOS, NAND is usually preferred over NOR, because a NAND puts its NMOS transistors in series, while a NOR stacks the slower PMOS transistors in series."

Code:
NOT A   = NAND(A, A)
A AND B = NAND(NAND(A, B), NAND(A, B))
A OR B  = NAND(NAND(A, A), NAND(B, B))
Red flag to avoid:

Not being able to derive the OR, or saying a gate is universal because it's cheap.

They may ask next:
  • How would you build an XOR from four NAND gates?
  • How would you use a Karnaugh map to simplify a four-input function before building it?
Say it in 60 seconds
Medium Technical round Fresher, Mid-level Practice question

10. A 3.3 volt microcontroller has to talk to a 5 volt logic chip. What can go wrong in each direction, and how do you fix it?

What the interviewer is really testing:
Whether you read input thresholds and absolute maximum ratings rather than assuming a high is a high.
Answer frame:

3.3 to 5: a 3.3 volt high may be below the 5 volt chip's minimum input high level.

5 to 3.3: a 5 volt signal can exceed the input rating and drive current through protection diodes.

Fixes: TTL-threshold inputs, level translators, dividers, or 5 volt tolerant pins.

Sample spoken answer:

"I look at the two directions separately. Going from 3.3 to 5 volts, the question is the receiver's input high threshold. A 5 volt CMOS input often wants about seven tenths of its supply, around 3.5 volts, so a 3.3 volt high may not be read reliably. If the chip has TTL-level inputs, like the HCT family, the threshold is around 2 volts and it's fine. Going from 5 down to 3.3, the risk is the microcontroller pin. Unless the datasheet says it's 5 volt tolerant, 5 volts drives current through its protection diodes into the 3.3 volt rail, which can damage it. For fixes, I'd use a proper level translator, a resistor divider for slow one-way signals, or a MOSFET-based shifter for an open-drain bus like I2C."

Red flag to avoid:

Saying 3.3 volts is always read as a high by 5 volt logic, or connecting 5 volts to any pin without checking.

They may ask next:
  • Why is a resistor divider a poor choice for a fast signal?
  • How does the single-MOSFET level shifter work on an I2C line?
Say it in 60 seconds
Medium Role knowledge round Fresher, Mid-level Practice question

11. From a hardware point of view, what does a microcontroller need around it on the board to start up and run reliably?

What the interviewer is really testing:
Whether you can design the support circuit for a chip from its datasheet, not just drop the chip on a schematic.
Answer frame:

Power: clean rails, decoupling at each pin, a filtered analog supply if it has one.

Clock and reset: crystal with the right load capacitors, a defined reset pin, boot pins strapped.

Access and protection: a programming or debug header, test points and protection on external connectors.

Sample spoken answer:

"I start with power. That means the right supply voltage, decoupling at every power pin, and if the chip has a separate analog supply or ADC reference pin, I filter that from the digital rail. Next is the clock. If it needs precise timing, I add a crystal with load capacitors calculated from the crystal's specified load, placed right at the pins. Then reset, so the reset pin sits in a defined state, often a pull-up with a small capacitor, plus any boot-mode pins strapped with resistors so it always boots from the right place. I always bring out the programming and debug pins to a header, add test points on the key rails, and put protection on anything that leaves the board, like a USB port or a sensor connector."

Red flag to avoid:

Leaving out the debug header or treating crystal load capacitors as any small value.

They may ask next:
  • How do you calculate the load capacitors for a crystal?
  • What happens if a boot-mode pin is left floating?
Say it in 60 seconds

Data Conversion 3 questions

Medium Technical round Fresher, Mid-level Practice question

12. A 12-bit ADC uses a 3.3 volt reference. What voltage is one step, and why do you put a filter in front of it?

What the interviewer is really testing:
Whether you can do the resolution sum and understand sampling and aliasing well enough to design the input.
Answer frame:

Step size: reference divided by 2 to the number of bits, about 0.8 millivolts here.

Sampling: sample faster than twice the highest frequency present, or it aliases.

Anti-alias filter: removes content above half the sample rate before the ADC sees it.

Sample spoken answer:

"One LSB is the reference divided by 2 to the 12th, so 3.3 volts over 4096, which is about 0.8 millivolts per step. That's the resolution on paper. The real accuracy also depends on the reference, noise and the ADC's own errors, so the effective bits are usually fewer than 12. The filter is about aliasing. The sampling theorem says I have to sample at more than twice the highest frequency in the signal. Anything above half the sample rate doesn't disappear. It folds back and shows up as a false lower frequency that I can't separate from the real signal afterwards. So I put a low-pass filter in front of the ADC with its cutoff well below half the sample rate, and I make sure its output can charge the ADC's sampling capacitor in time."

Red flag to avoid:

Believing the filter can be added later in software, or quoting 12-bit resolution as 12-bit accuracy.

They may ask next:
  • Why can a high source impedance cause errors on a SAR ADC input?
  • How does averaging many samples help, and what can it not fix?
Say it in 60 seconds
Medium Technical round Fresher, Mid-level Practice question

13. How does an R-2R ladder DAC work, and how would you get an analog voltage out of a microcontroller that has no DAC?

What the interviewer is really testing:
Whether you understand how a DAC builds a voltage from bits, and know the common PWM-and-filter workaround and its trade-off.
Answer frame:

R-2R: each bit switches its leg between reference and ground, contributing a binary-weighted share.

Output: reference times the code over 2 to the number of bits.

No DAC: filter a PWM output with a low-pass, trading ripple against response time.

Sample spoken answer:

"An R-2R ladder uses only two resistor values. Each bit drives a 2R leg that's switched to either the reference or ground, and the ladder is arranged so each bit contributes half as much as the one above it. The output ends up as the reference times the digital code divided by 2 to the number of bits. The nice part is you only need two well-matched values. On a microcontroller with no DAC, I'd use PWM and a low-pass filter. The average of a PWM signal is the duty cycle times the high voltage, and the filter strips out the switching. The trade-off is ripple against speed. A lower cutoff gives a smoother output but responds slowly to changes, so I'd run the PWM as fast as the resolution allows and maybe use a second-order filter."

Red flag to avoid:

Saying PWM is already an analog voltage with no filtering needed.

They may ask next:
  • What limits the accuracy of an R-2R ladder built from discrete resistors?
  • How does PWM frequency trade against resolution on a timer?
Say it in 60 seconds
Medium Situational round Fresher, Mid-level Practice question

14. A sensor reading from the ADC jumps around by several counts even though the input should be steady. How do you track down the noise?

What the interviewer is really testing:
Whether you can separate noise from the sensor, the analog path, the reference and the digital side, instead of just averaging it away.
Answer frame:

Baseline: short the input or use a known voltage to see the ADC's own noise.

Look for the pattern: use a scope and a capture of the samples to see if the noise is random or tied to a clock or supply.

Fix at the source: reference, grounding, filtering and source impedance, then average only what's left.

Sample spoken answer:

"First, I'd find out where the noise enters. I'd replace the sensor with a clean, known voltage, or short the input to ground, and see how much the reading still moves. That tells me if the ADC and reference are the problem, or the sensor path. Then I'd capture a few thousand samples and look at them. Random noise looks very different from noise at a fixed frequency, and a fixed frequency usually points to a switching regulator, a clock or a motor. I'd put the scope on the reference and the analog supply and look for ripple there. Common fixes are a cleaner reference, better filtering on the analog supply, an RC right at the ADC pin, a lower source impedance, and sampling when noisy parts aren't switching. Averaging comes last, for whatever random noise is left."

Red flag to avoid:

Going straight to averaging in software without asking where the noise comes from.

They may ask next:
  • The noise gets worse only when the radio transmits. What does that suggest?
  • Why can a high-value resistor divider in front of the ADC cause errors?
Say it in 60 seconds

Power Supplies 3 questions

Easy Technical round Fresher, Mid-level Practice question

15. You need 3.3 volts at 500 milliamps from a 12 volt input. Would you use a linear regulator or a buck converter, and why?

What the interviewer is really testing:
Whether you work out the power dissipation before choosing, and know what each regulator costs you.
Answer frame:

Linear loss: the voltage drop times the current becomes heat.

Numbers here: 8.7 volts times 0.5 amps is about 4.35 watts, too much.

Buck trade-off: far less heat, but switching noise, more parts and layout care.

Sample spoken answer:

"I'd do the power sum first. A linear regulator drops the difference as heat, so that's 12 minus 3.3, which is 8.7 volts, times half an amp, about 4.35 watts. That's more than twice the power the load actually uses, and a small regulator would need a big heatsink or would shut down. So here I'd use a buck converter, which converts the voltage by switching and wastes much less. The price is switching ripple and noise, an inductor, more careful layout, and some EMI work. If a sensitive analog block needs a very clean rail, I might follow the buck with a small low-dropout linear regulator, which only drops a few hundred millivolts and cleans up the ripple without much heat."

Red flag to avoid:

Picking a linear regulator without calculating the heat, or saying a buck converter is always better.

They may ask next:
  • When would a linear regulator be the better choice?
  • What does dropout voltage mean on an LDO?
Say it in 60 seconds
Hard Technical round Mid-level, Senior Practice question

16. Explain how a buck converter works, and tell me which parts of its PCB layout matter most.

What the interviewer is really testing:
Whether you understand the switching action and the current loops well enough to lay one out so it's quiet and stable.
Answer frame:

Operation: a switch chops the input, the inductor and output capacitor average it; duty cycle is roughly Vout over Vin.

Hot loop: input capacitor, high-side switch and low-side switch carry pulsed current; keep that loop tiny.

Sensitive parts: small switch node, feedback divider close to the chip and away from noise, solid ground.

Sample spoken answer:

"A buck converter switches the input on and off into an inductor. When the switch is on, the inductor current ramps up and feeds the load. When it's off, the low-side switch or diode keeps the current flowing and it ramps down. The output capacitor smooths the ripple, and in steady state the duty cycle is roughly output over input voltage. For layout, the most important thing is the loop through the input capacitor, the high-side switch and the low-side switch, because the current there turns on and off sharply every cycle. I keep that loop as small as possible, with the input capacitor right at the chip. I keep the switch node copper small, since it radiates, and I route the feedback divider close to the chip, away from the inductor and switch node, sensing at the output."

Red flag to avoid:

Describing the output loop as the critical one and placing the input capacitor wherever it fits.

They may ask next:
  • What happens to the inductor current at very light load?
  • Why does a long trace to the input capacitor cause ringing on the switch node?
Say it in 60 seconds
Hard Technical round Mid-level, Senior Practice question

17. A MOSFET runs cool when you switch a load on and leave it, but gets hot when you drive it with fast PWM. Why, and what would you change?

What the interviewer is really testing:
Whether you can separate conduction loss from switching loss and connect switching loss to gate drive.
Answer frame:

Conduction loss: current squared times on-resistance, present at DC too.

Switching loss: each transition spends time with high voltage and high current together, and it scales with frequency.

Fixes: stronger gate drive, lower frequency, a better-suited part, or better cooling.

Sample spoken answer:

"When it's just on, the only loss is conduction loss, the current squared times the on-resistance, and that's small for a good part. With PWM I add switching loss. During every turn-on and turn-off there's a short time when the device has both a large voltage across it and a large current through it, and that energy is lost each transition, so the loss grows with frequency. The usual cause of slow transitions is weak gate drive. A microcontroller pin can only source a small current, so it takes a long time to charge the gate. It may not fully enhance the MOSFET at 3.3 volts either. I'd add a proper gate driver, check the gate charge in the datasheet, lower the PWM frequency if the application allows, and remember on-resistance rises as the part heats up."

Red flag to avoid:

Blaming only the on-resistance and picking a bigger MOSFET, which can make the gate even slower to drive.

They may ask next:
  • How would you estimate the switching loss from the datasheet?
  • What role does the body diode play in a half-bridge?
Say it in 60 seconds

PCB and Signal Integrity 4 questions

Easy Technical round Fresher, Mid-level Practice question

18. Why does nearly every chip on a board have small capacitors right next to its power pins, and how do you place them?

What the interviewer is really testing:
Whether you understand decoupling as a local charge supply and know that placement and loop inductance matter more than the value.
Answer frame:

Purpose: supply fast current spikes locally so the rail doesn't dip or spread noise.

Mix: small ceramics at each pin, plus bulk capacitance nearby.

Placement: as close as possible, short wide connections, vias straight to the planes.

Sample spoken answer:

"When a digital chip switches, it pulls short bursts of current. The supply further away can't deliver them fast because of the inductance of the traces between them. The decoupling capacitor sits right at the pin and supplies that burst locally, so the rail doesn't dip and the noise doesn't spread across the board. Usually I put a small ceramic, often 100 nanofarads, at each power pin, and a larger bulk capacitor nearby for slower changes. Placement matters more than the exact value. I put the capacitor as close to the pin as I can, keep the connection short, and drop vias straight to the power and ground planes. A capacitor at the end of a long, thin trace barely helps, because the trace inductance cancels out its benefit at high frequency."

Red flag to avoid:

Treating decoupling as a value to copy from a reference design while ignoring where the capacitor sits.

They may ask next:
  • Why do people sometimes mix several capacitor values on one rail?
  • What changes for an analog supply pin compared with a digital one?
Say it in 60 seconds
Hard Technical round Mid-level, Senior Practice question

19. When does a PCB trace need to be treated as a transmission line, and what do you do about it in the layout?

What the interviewer is really testing:
Whether you understand that edge rate, not clock frequency, decides it, and know impedance, termination and return paths.
Answer frame:

When: the trace delay becomes a meaningful fraction of the signal's rise time.

Controlled impedance: set by trace width, dielectric height and material, agreed with the fab via the stack-up.

Keep it clean: termination to stop reflections and an unbroken reference plane for the return current.

Sample spoken answer:

"It's the edge speed that matters, not the clock rate. A slow clock with very fast edges can still ring. Signals on ordinary FR-4 travel at roughly 15 centimetres per nanosecond. Once the trace delay is more than a small fraction of the rise time, a common rule of thumb says about a sixth, reflections from impedance changes start to show up as ringing and overshoot. Then I treat it as a transmission line. I design the trace to a target impedance, often 50 ohms single-ended, by setting width against the stack-up the fab confirms. I terminate it, usually a series resistor at the driver for point-to-point lines. And I route it over a solid reference plane, because the return current flows right under the trace. Crossing a gap in that plane forces a detour, which causes ringing and radiation."

Red flag to avoid:

Saying it only matters above some clock frequency, or ignoring where the return current flows.

They may ask next:
  • Why does a series termination resistor work for a point-to-point line?
  • What happens to a signal routed across a split between two ground areas?
Say it in 60 seconds
Medium Technical round Fresher, Mid-level Practice question

20. Why do long cable runs in noisy places use differential signalling like RS-485 instead of a plain single-ended UART signal?

What the interviewer is really testing:
Whether you understand common-mode noise rejection and the practical wiring rules of a differential bus.
Answer frame:

Differential: the receiver reads the difference between two wires, so noise hitting both cancels.

Ground offset: it tolerates a difference in ground voltage between distant ends, within its common-mode range.

Wiring: twisted pair, termination at both ends of the bus, bias for a defined idle state.

Sample spoken answer:

"A single-ended signal is measured against ground, so any noise picked up along the cable or any difference in ground voltage between the two ends lands directly on the signal. With a differential pair, the transmitter drives two wires in opposite directions and the receiver only looks at the difference between them. Noise from a motor or a long cable run tends to hit both wires equally, so it cancels out. That's why RS-485 can run over long distances and let several nodes share one pair. To get that benefit, I use twisted pair cable, put termination resistors matching the cable impedance at the two far ends of the bus, not on every node, and add biasing so the line sits in a known state when nobody is transmitting."

Red flag to avoid:

Saying differential signalling just means using two wires for more current, or terminating every node.

They may ask next:
  • What goes wrong if you put a termination resistor on every node?
  • Why do many RS-485 designs add isolation between the transceiver and the rest of the board?
Say it in 60 seconds
Hard Situational round Mid-level, Senior Practice question

21. Your product fails its radiated emissions test a few weeks before launch, with a spike at one frequency. How do you approach it?

What the interviewer is really testing:
Whether you can find the source of an emissions problem systematically and fix it with the least change to the design.
Answer frame:

Identify: match the frequency to clocks, switching regulators and their harmonics.

Locate: use a near-field probe and cables to find what's radiating.

Fix and verify: the smallest change first, like filtering, snubbing or edge slowing, then pre-scan before retesting.

Sample spoken answer:

"I'd start with the frequency. I'd list every clock, switching regulator and fast interface on the board and check whether the spike is one of them or a harmonic. Then I'd find where it's coming from. I'd use a near-field probe on a spectrum analyser to scan the board, and I'd check the cables, because a cable acting as an antenna is a very common cause. If unplugging a cable changes the spike, that's a strong clue. For the fix, I'd try the least invasive options first, like a ferrite or common-mode choke on the cable, a series resistor to slow a fast edge, a snubber on a switch node, or spread-spectrum if the clock allows it. I'd pre-scan each change myself before booking the lab again, and note which fixes need a layout change for the next revision."

Red flag to avoid:

Adding shielding everywhere and hoping, with no attempt to find the source.

They may ask next:
  • The spike only appears with one cable plugged in. What does that tell you?
  • Which fixes would you keep for production and which are only temporary?
Say it in 60 seconds

Test and Debug 4 questions

Medium Role knowledge round Fresher, Mid-level, Senior Practice question

22. How do you set up an oscilloscope and probe to measure a fast edge or supply ripple without the measurement lying to you?

What the interviewer is really testing:
Whether you know how the probe and scope themselves distort a measurement, which separates real bench experience from theory.
Answer frame:

Bandwidth: the scope and probe must be fast enough for the edge you're measuring.

Probe: compensate the 10x probe, and replace the long ground lead with a short spring tip.

Ripple: AC coupling, bandwidth limit, probe right at the output capacitor.

Sample spoken answer:

"First, I check bandwidth. A rough rule is that the rise time a system can show is about 0.35 divided by its bandwidth, so a 100 megahertz scope can't show edges much faster than about 3.5 nanoseconds. Next is the probe. I compensate a 10x probe on the scope's calibration square wave, and for fast edges I drop the long ground clip. That clip forms an inductive loop that adds ringing that isn't really on the board, so I use a short spring ground right at the point I'm measuring. For supply ripple, I use AC coupling so I can zoom in, turn on the bandwidth limit if I only care about low-frequency ripple, and measure right across the output capacitor with that short ground, so I'm not picking up the switching noise through the air."

Red flag to avoid:

Blaming the circuit for ringing you created with a long ground lead.

They may ask next:
  • Why is it dangerous to clip the probe ground onto a node that isn't ground?
  • How would you measure current with a scope?
Say it in 60 seconds
Easy Role knowledge round Fresher, Mid-level Practice question

23. How do you measure a board's current with a multimeter, and what mistakes give you a wrong reading or blow the meter's fuse?

What the interviewer is really testing:
Whether you've actually used a meter on a bench and know how it changes the circuit it measures.
Answer frame:

Series, not parallel: break the circuit, move the lead to the current jack and pick a range.

Burden voltage: the meter's shunt drops voltage, which can upset a low-voltage circuit.

Common mistakes: leaving the lead in the current jack, measuring resistance with power on or in circuit.

Sample spoken answer:

"Current is measured in series, so I break the supply path, often at a jumper or by lifting a link, move the red lead to the current jack, and start on a high range. The catch is that the meter measures current through a small internal resistor, so it drops some voltage, which is called burden voltage. On a microamp range that drop can be large enough to make a 3.3 volt microcontroller brown out when it wakes up, so the reading looks odd or the board resets. The classic mistake is leaving the lead in the current jack and then touching it across a supply to measure voltage. That's a dead short through the meter and it blows the fuse. I also only measure resistance with power off, and remember that in circuit I'm reading every parallel path too."

Red flag to avoid:

Putting the meter across the supply to read current, or not knowing the meter itself changes the circuit.

They may ask next:
  • How would you measure a sleep current that jumps to hundreds of milliamps when the device wakes?
  • Why can two meters show different readings on a PWM or non-sinusoidal signal?
Say it in 60 seconds
Hard Behavioral round Mid-level, Senior Practice question

24. Tell me about the hardest hardware fault you've tracked down. How did you narrow it from the whole board to one cause?

What the interviewer is really testing:
Whether you debug with a method, making hypotheses and cutting the problem in half, rather than by swapping parts until it works.
Answer frame:

Symptom: what failed, how often, and why it was hard.

Narrowing: the measurements and experiments that ruled things out.

Root cause and fix: what it really was and how you proved it.

Sample spoken answer:

"At my last company, a motor controller board would randomly reset, maybe once an hour, and only with the motor under load. Firmware was the first suspect, but the reset flags showed a brownout, so I moved to power. I put the scope on the 3.3 volt rail and triggered on a dip, and I caught short drops each time the motor current stepped up. The regulator itself was fine. The cause was the layout. The motor's return current shared a thin ground path with the logic supply, so every current spike lifted the logic ground. I proved it by adding a thick jumper wire to separate the returns, and the resets stopped completely. On the next revision, we split the high-current return and joined the grounds at one point near the input."

Red flag to avoid:

A story where the fix came from swapping random parts, with no measurement that proved the cause.

They may ask next:
  • What would you have done if you couldn't catch the dip on the scope?
  • How did you make sure the fix didn't create a new problem?
Say it in 60 seconds
Hard Situational round Fresher, Mid-level, Senior Practice question

25. A new board comes back from assembly and draws far too much current the moment you power it. Walk me through how you find the fault.

What the interviewer is really testing:
Whether you protect the board first, then narrow the fault down rail by rail with a clear method.
Answer frame:

Protect: power off, then retry only from a current-limited supply.

Look and measure: inspect for orientation and solder faults, measure each rail's resistance to ground.

Isolate: find the hot part, split rails at links or regulators, compare with a second board.

Sample spoken answer:

"First, I'd switch it off and only power it again from a bench supply with a low current limit, so nothing burns while I look. Then I'd inspect it under magnification, checking the orientation of diodes, polarised capacitors and ICs, and looking for solder bridges, especially on fine-pitch parts. Next, with power off, I'd measure the resistance from each rail to ground and compare against a known-good board or what I expect. A very low reading tells me which rail to chase. With the current limited, I'd look for the part that heats up, using a thermal camera or a careful finger. If the rails are joined, I'd lift a zero-ohm link or a regulator output to split them. I'd also check whether a second board from the same batch shows the same fault."

Red flag to avoid:

Turning the supply up to 'see what happens', or starting to swap parts before measuring anything.

They may ask next:
  • The short is on a rail with twenty parts on it. How do you find which one?
  • What would it mean if every board in the batch had the same fault?
Say it in 60 seconds

Design Process 3 questions

Medium Behavioral round Fresher, Mid-level, Senior Practice question

26. Tell me about a design mistake of yours that made it onto a fabricated board. How was it caught, and what did you change in how you work?

What the interviewer is really testing:
Whether you own mistakes plainly and turned one into a lasting change in your checks.
Answer frame:

Mistake: what it was, stated plainly.

Impact: how it was found and what it cost in time or boards.

Change: the check or habit you added so it doesn't happen again.

Sample spoken answer:

"On one board, I used a voltage regulator footprint from our library without checking the pin order against the datasheet. That footprint was for a different variant with the input and output swapped. It was caught at bring-up when the rail came up wrong on the first board I powered, and luckily I was using a current-limited supply, so nothing burned. We fixed the prototypes by lifting and rewiring the part, which cost a couple of days, and the next spin fixed it properly. What I changed is that I now check every new or reused footprint against the actual datasheet pinout, and I print the power section and trace each rail by hand before sending files out. I also power every new board from a current-limited supply first."

Red flag to avoid:

Picking a mistake that was really someone else's fault, or one with no change in process after.

They may ask next:
  • What else is on your checklist before you release a board for fabrication?
  • How did you tell your team about the mistake?
Say it in 60 seconds
Medium Behavioral round Mid-level, Senior Practice question

27. Tell me about a time a key component went out of stock or end-of-life and you had to design around it. What did you check before accepting a substitute?

What the interviewer is really testing:
Whether you qualify a replacement part properly rather than trusting that 'same function' means 'drop-in'.
Answer frame:

Situation: which part, and the pressure on the schedule.

Checks: pinout, electrical specs, behaviour at the corners, and testing on real boards.

Result: what you shipped and what you did to reduce the risk next time.

Sample spoken answer:

"In my last role, the op-amp on our sensor board went on long allocation right before a production run. The distributor offered a pin-compatible part from another maker. I didn't assume it was drop-in. I compared the datasheets line by line, including input offset, bias current, output swing near the rails and stability with our capacitive load, and found its input bias current was much higher, which mattered because we had a high-value resistor in the input path. I tested it on a few boards anyway, and the offset error was visible. So I picked a different substitute with a lower bias current, tested it across temperature on the bench, and got it approved. Afterwards we started listing a checked second source for critical parts on every new design."

Red flag to avoid:

Swapping in a 'compatible' part from pinout alone with no electrical check or test.

They may ask next:
  • How do you decide which parts on a board need a second source?
  • How would you test a substitute if you had only two days?
Say it in 60 seconds
Medium Situational round Mid-level, Senior Practice question

28. Your manager wants to ship the first production batch with a hand-soldered wire fix on every board because the next PCB revision is late. What do you do?

What the interviewer is really testing:
Whether you can weigh reliability risk against schedule honestly and propose a controlled way forward instead of a flat yes or no.
Answer frame:

Assess risk: what the wire carries and how it could fail with vibration, heat or handling.

Control it: a written rework instruction, fixing and inspection, and testing on reworked boards.

Decide openly: put the risk in writing and agree on when the proper revision takes over.

Sample spoken answer:

"I wouldn't say no by reflex, because reworked boards do ship sometimes. It depends on what that wire is doing. First, I'd look at the risk. Is it a low-speed signal or a power path, and will the product see vibration or temperature swings that could break the joint? If it's reasonable, I'd make it controlled. That means a written rework instruction with photos, the wire glued down so it can't flex, a clear inspection step, and a sample of reworked boards through the same stress testing as normal. I'd also want the batch size limited and the date for the new revision agreed. If the wire carries a fast signal or high current, I'd show my manager why the risk of field failures outweighs the delay, and suggest shipping fewer units first."

Red flag to avoid:

Either agreeing silently with no controls, or refusing without looking at the actual risk.

They may ask next:
  • What would make you refuse outright?
  • How would you track which units in the field have the rework?
Say it in 60 seconds

Teamwork 4 questions

Medium Behavioral round Mid-level, Senior Practice question

29. Tell me about a time you disagreed with a firmware or layout engineer about how something on a board should be done. How was it settled?

What the interviewer is really testing:
Whether you can argue a hardware point with data and still work well with the people on the other side.
Answer frame:

Disagreement: what each side wanted and why.

How you handled it: evidence, test or trade-off you brought.

Outcome: what was decided and how the relationship stayed.

Sample spoken answer:

"At my last company, the firmware engineer wanted every spare pin routed to a header so he'd have flexibility, and I wanted to keep the board small and the routing clean around a sensitive ADC. We were both right about something. Instead of arguing in the abstract, I sat with him and we went through what he actually expected to need. It came down to a debug UART, two spare GPIOs and a test pad on the reset line. I routed those to a small header away from the analog section and left the rest unrouted. He got what he actually needed, the analog layout stayed clean, and afterwards he started bringing his pin requests to the schematic review early, which saved us both time."

Red flag to avoid:

A story where you simply overruled the other person, or where the disagreement is still going.

They may ask next:
  • What would you have done if you couldn't reach agreement?
  • How do you make sure firmware needs are captured before layout starts?
Say it in 60 seconds
Easy Behavioral round Fresher, Mid-level, Senior Practice question

30. Tell me about a time you had to explain a hardware problem or a design trade-off to someone who isn't an engineer, like a product manager or a customer.

What the interviewer is really testing:
Whether you can drop the jargon and explain impact and choices in terms of time, cost and risk.
Answer frame:

Context: who needed to understand and what decision they had to make.

Translation: how you explained it without jargon.

Result: what they decided and whether it worked.

Sample spoken answer:

"Our product manager wanted to know why a board revision would push the schedule back by three weeks for what looked like a tiny change. The real issue was that the new radio module needed a different antenna layout, which meant new boards, new testing and a repeat of the emissions test. Instead of talking about ground planes, I drew the board on a whiteboard, showed which area had to change, and listed the three steps that each took about a week. Then I gave him two options, ship the old module now or wait for the better range. Once he saw the choice in terms of time and what the customer would get, he decided in the meeting, and he later asked me to join the customer call to explain it."

Red flag to avoid:

Blaming the listener for not understanding, or explaining with more jargon.

They may ask next:
  • How do you explain uncertainty when you can't yet give a firm date?
  • What's a mistake engineers often make in these conversations?
Say it in 60 seconds
Easy Culture fit round Fresher, Mid-level, Senior Practice question

31. What does a good schematic or layout review look like to you, and how do you react when someone picks your design apart?

What the interviewer is really testing:
Whether you see reviews as a way to catch mistakes cheaply, and take criticism of your work without getting defensive.
Answer frame:

Before: share the design early with the requirements and your open questions.

During: go through power, interfaces, footprints and testability, and welcome hard questions.

After: track every comment to closed, and thank people who found problems.

Sample spoken answer:

"To me, a good review happens early enough that changes are still cheap. I send the schematic with the requirements and a short list of the things I'm least sure about, so people spend their time where it matters. In the review, we go through the power tree, every connector and interface, footprints for new parts, and whether the board can be tested and debugged. I honestly want people to pick it apart, because a comment in a review costs an hour, and the same mistake on a fabricated board costs weeks. If I disagree with a comment, I explain my reasoning, but I don't take it personally. After the review, I log every comment and close each one, so nothing gets lost before release."

Red flag to avoid:

Treating reviews as a formality or getting defensive when someone finds a real problem.

They may ask next:
  • What's the best catch someone made in a review of your work?
  • How do you give critical feedback on a senior engineer's design?
Say it in 60 seconds
Easy Culture fit round Fresher, Mid-level, Senior Practice question

32. How do you keep yourself and others safe on the bench when you're working near mains voltage or large charged capacitors?

What the interviewer is really testing:
Whether safety is a habit you actually practise in the lab, not a rule you only know about.
Answer frame:

Before: isolate supplies, and know where the stored energy is on the board.

While working: discharge and verify with a meter, use isolation or proper differential probes, one hand where you can.

Team: label live setups, never leave them unattended, and speak up when you see risk.

Sample spoken answer:

"I treat anything connected to mains as dangerous until I've proven it isn't. Before I touch a board, I switch off and unplug it, and I remember that big capacitors can hold a charge long after power is gone. So I discharge them through a proper resistor and then check with a meter before touching anything. When I have to measure a live mains circuit, I use an isolation transformer or a proper differential probe, not a normal scope probe with the ground clip on the wrong node. I keep one hand out of the circuit where I can. For the team, I label live setups clearly and never leave one running unattended. If I see someone working in a way that looks risky, I say so, even if they're more senior."

Red flag to avoid:

Saying you're careful without naming a single concrete habit, or treating capacitors as safe once power is off.

They may ask next:
  • Why is floating the scope by removing its earth pin a bad idea?
  • What would you check before powering up someone else's setup?
Say it in 60 seconds
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For the call itself

The questions above are the prep. The call has ten more.

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